The present disclosure relates generally to the electrical, electronic and computer arts and, more particularly, to gate metal patterning of structures including adjoining nFET and pFET regions and CMOS devices including dual metal gates.
With shrinking dimensions of various integrated circuit components, transistors such as field-effect transistors (FETs) have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Metal oxide semiconductor field-effect transistors (MOSFETs) are well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease. In metal gate CMOS technology, two different metals can be employed as gate metal for p-type and n-type MOSFETs, respectively, each having a different work function for determining transistor threshold voltage. After blanket deposition of a first gate metal layer on both nFET and pFET regions of a structure, the first gate metal is selectively removed from one of the regions. A second gate metal is then deposited over the entire structure. The gate electrodes are then patterned.
Nanosheet FETs have been under development for possible use in tight pitch applications such as 7 nm nodes and beyond. Such FETs include multiple channel layers, each channel layer being separated by a gate stack including a layer of electrically conductive gate material and a gate dielectric layer. The gate stacks wrap around all sides of the channel layers, thereby forming a gate-all-around (GAA) structure. Epitaxial regions on the ends of the nanosheet channel layers form source/drain regions of the nanosheet FETs.